• DocumentCode
    1049999
  • Title

    High-efficiency enhancement-mode power heterojunction FET with buried p/sup +/-GaAs gate structure for low-voltage-operated mobile applications

  • Author

    Bito, Yasunori ; Yamakawa, Yoshiaki ; Tanaka, Shinichi ; Iwata, Naotaka

  • Author_Institution
    NEC Compound Semiconductor Devices, Ltd, Otsu
  • Volume
    27
  • Issue
    8
  • fYear
    2006
  • Firstpage
    636
  • Lastpage
    639
  • Abstract
    This letter describes a successfully developed enhancement-mode double-doped AlGaAs/InGaAs/AlGaAs heterojunction FET with a buried p+-n junction gate structure for low-voltage-operated mobile applications. The buried p+-GaAs gate structure effectively reduced on-resistance (Ron) and suppressed drain-current frequency dispersion for the device with high positive threshold voltage, resulting in high-efficiency characteristics under low-voltage operation. The fabricated p+-gate HJFET exhibited a low Ron of 1.4 Omegamiddotmm with a threshold voltage of +0.4 V. Negligible frequency dispersion characteristics were obtained through pulsed current-voltage measurements for the device. Under a single 2.7-V operation, a 19.8-mm gate width device exhibited a power added efficiency of 51.9% with 26.8-dBm output power and a -40.1-dBc adjacent channel power ratio using a 1.95-GHz wideband code-division multiple-access signal
  • Keywords
    III-V semiconductors; aluminium compounds; field effect transistors; gallium arsenide; indium compounds; thermal stability; 1.4 ohm; 1.95 GHz; 19.8 mm; 2.7 V; AlGaAs-InGaAs-AlGaAs; buried gate structure; buried junction gate structure; drain-current frequency dispersion; enhancement-mode power heterojunction FET; frequency dispersion characteristics; high positive threshold voltage; low-voltage-operated mobile applications; pulsed current-voltage measurements; Current measurement; Dispersion; Double-gate FETs; Frequency measurement; Heterojunctions; Indium gallium arsenide; Power generation; Pulse measurements; Threshold voltage; Wideband; Buried gate; enhancement mode; heterojunction FET; high efficiency; low-voltage operation;
  • fLanguage
    English
  • Journal_Title
    Electron Device Letters, IEEE
  • Publisher
    ieee
  • ISSN
    0741-3106
  • Type

    jour

  • DOI
    10.1109/LED.2006.879043
  • Filename
    1661715