Title :
An integrated CMOS mixed-mode signal processor for disk drive read channel applications
Author :
Kim, Beomsup ; Greco, Joseph D. ; Yang, Howard C. ; Wu, Wen-Chung S. ; Chowdhury, Rahim F.
Author_Institution :
Philips Res., Palo Alto, CA, USA
fDate :
1/1/1994 12:00:00 AM
Abstract :
A read channel processor architecture for Winchester disk drive applications is presented, designed to operate with data rates from 10 to 32 Mbits/sec with (1,7) Run Length Limited (RLL) encoding on a 5 volt 1-μm CMOS technology. The processor performs the functions of pulse detection and data separation using integrated CMOS analog amplifiers and filters and a digital phase-locked loop (PLL). It integrates many of the functions previously performed with discrete components and has enhanced programmability to more fully support Zoned Bit Recording (ZBR). This paper presents an architectural overview of the processor with comparisons to existing solutions, detailing the system constraints of the architecture. Unique CMOS circuit designs are presented along with the pipelined architecture of the digital PLL
Keywords :
CMOS integrated circuits; analogue processing circuits; digital signal processing chips; hard discs; mixed analogue-digital integrated circuits; phase locked loops; pipeline processing; (1,7) run length limited encoding; 1 mum; 10 to 32 Mbit/s; 5 V; CMOS analog filters; CMOS circuit designs; CMOS mixed-mode signal processor; Winchester disk drive; data rates; data separation; digital phase-locked loop; disk drive read channel; integrated CMOS analog amplifiers; pipelined architecture; pulse detection; read channel processor architecture; zoned bit recording; CMOS process; CMOS technology; Digital filters; Disk drives; Disk recording; Phase detection; Phase locked loops; Pulse amplifiers; Signal processing; Winches;
Journal_Title :
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
