Title :
A 90-nm Power Optimization Methodology With Application to the ARM 1136JF-S Microprocessor
Author :
Khan, Aurangzeb ; Watson, Philip ; Kuo, George ; Le, Due ; Nguyen, Trung ; Yang, Steven ; Bennett, Peter ; Huang, Pokai ; Gill, Jaspal ; Hawkins, Chris ; Goodenough, John ; Wang, Demin ; Ahmed, Irfan ; Tran, Peter ; Mak, Helder ; Kim, Oanh ; Martin, Frank
Author_Institution :
Cadence Design Syst. Inc., San Jose, CA
Abstract :
An electrical and physical design power optimization methodology and design techniques developed to create an IC with an ARM 1136JF-S microprocessor in 90-nm standard CMOS are presented. Design technology and methodology enhancements to enable multiple supply voltage operation, leakage current and clock rate optimization, single-pass RTL synthesis, VDD selection, power optimization and timing and electrical closure in a multi-VDD domain design are described. A 40% reduction in dynamic and a 46% reduction in leakage power dissipation has been achieved while maintaining a 355-MHz operating clock rate under typical conditions. Functional and electrical design requirements were achieved with the first silicon
Keywords :
CMOS digital integrated circuits; integrated circuit design; logic design; microprocessor chips; 355 MHz; 90 nm; ARM 1136JF-S microprocessor; clock rate optimization; leakage current; leakage power dissipation; multiple supply voltage operation; power optimization methodology; single-pass RTL synthesis; CMOS integrated circuits; CMOS technology; Clocks; Design methodology; Design optimization; Leakage current; Microprocessors; Optimization methods; Standards development; Voltage; Circuit synthesis; design automation; design methodology; digital systems; electronics industry; integrated circuit design; integrated circuit manufacture; power distribution control;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2006.877248
