Title :
3-D Silicon Integration and Silicon Packaging Technology Using Silicon Through-Vias
Author :
Knickerbocker, John U. ; Patel, Chirag S. ; Andry, Paul S. ; Tsang, Cornelia K. ; Buchwalter, L. Paivikki ; Sprogis, Edmund J. ; Gan, Hua ; Horton, Raymond R. ; Polastre, Robert J. ; Wright, Steven L. ; Cotte, John M.
Author_Institution :
IBM T. J. Watson Res. Center, Yorktown Heights, NY
Abstract :
System-on-Chip (SOC) and System-on-Package (SOP) technologies each have advantages depending on application needs. As system architects and designers leverage ever-increasing CMOS technology densities, a range of two- and three-dimensional silicon integration technologies are emerging which will likely support next-generation high-volume electronic applications and may serve high-performance computing applications. This paper will discuss a few emerging technologies which offer opportunities for enhanced circuit performance, or reduced power as one example. Silicon-on-silicon integration may include three-dimensional (3-D) integration on-chip or may leverage chip stacking or chip integration on package. Common technology features include silicon through-vias, high-I/O interconnection and silicon-on-silicon either as 3-D integrated circuits, integrated chip stacks or silicon-on-silicon packages with passive function or high-bandwidth wiring. Silicon chips on silicon interposers with integrated function such as decoupling capacitors may provide a better module architecture compared to increased on-chip decoupling or off chip discrete capacitors mounted on package at the chip perimeter or underside of the package. Advanced silicon carrier package technology with fine pitch (50 mum) interconnection is described. This silicon carrier package contains silicon through-vias and offers >16times increase over standard chip I/O, a 20times to 100times increase in wiring density over traditional organic and ceramic packaging, and allows for integrated high-performance passives. Silicon carrier technology supports lithographic scaling and provides a basis for known good die (KGD) wafer testing. It may be considered for use in a number of applications including optoelectronic (OE) transceivers, silicon interposers with integrated decoupling capacitors, and mini-multi-chip modules (MMCMs) which integrate heterogeneous dies forming a single "virtual chip."
Keywords :
elemental semiconductors; fine-pitch technology; integrated circuit interconnections; integrated circuit packaging; silicon; 3D integrated circuits; 3D integration on-chip; 3D silicon integration; 50 micron; CMOS technology densities; KGD wafer testing; MMCM; SOC technologies; SOP technologies; Si; ceramic packaging; chip integration on package; chip stacking; die wafer testing; fine pitch interconnection; heterogeneous dies; high-bandwidth wiring; integrated decoupling capacitors; mini-multi-chip modules; off chip discrete capacitors; on-chip decoupling; optoelectronic transceivers; organic packaging; silicon carrier package technology; silicon chips; silicon interposers; silicon packaging technology; silicon through-vias; silicon-on-silicon integration; silicon-on-silicon packages; system-on-chip technologies; system-on-package technologies; virtual chip; CMOS technology; Capacitors; Computer applications; Electronics packaging; Integrated circuit interconnections; Integrated circuit packaging; Integrated circuit technology; Silicon; System-on-a-chip; Wiring; 3-D; Chip integration; high bandwidth; integrated decoupling capacitors; interconnection; silicon packaging; silicon through-vias;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2006.877252
