A Highly Integrated CMOS Analog Baseband Transceiver With 180 MSPS 13-bit Pipelined CMOS ADC and Dual 12-bit DACs

Author

Gulati, Kush ; Peng, Mark Shane ; Pulincherry, Anurag ; Munoz, Carlos E. ; Lugin, Mike ; Bugeja, Alex R. ; Li, Jipeng ; Chandrakasan, Anantha P.

Author_Institution

Bitwave Semicond., Lowell, MA

Volume

41

Issue

8

fYear

2006

Firstpage

1856

Lastpage

1866

Abstract

A CMOS analog baseband transceiver with a 13-bit, 180 MSPS pipelined ADC and dual 12-bit, 180 MSPS current-steering DACs is presented. The ADC is implemented without a dedicated track-and-hold stage, utilizes a front-end 2.5-bit stage with matched MDAC/comparator tracking circuits, and demonstrates an ENOB of 10.6 bits at 15 MHz and 9.7 bits at 100 MHz, employing a low-jitter delay-lock loop for its phasing. The dual I/Q DACs show over 62 dB SFDR over the Nyquist band by utilizing a dynamic linearity enhancing architecture

Keywords

CMOS analogue integrated circuits; analogue-digital conversion; comparators (circuits); delay lock loops; digital-analogue conversion; sample and hold circuits; transceivers; 100 MHz; 12 bit; 13 bit; 15 MHz; CMOS analog baseband transceiver; ENOB; MDAC circuits; Nyquist band; SFDR; comparator tracking circuits; current-steering DAC; dual I-Q DAC; dynamic linearity enhancing architecture; low-jitter delay-lock loop; pipelined CMOS ADC; Baseband; Delay; Digital-analog conversion; Linearity; Liquid crystal displays; Packaging; Pipelines; Tracking loops; Transceivers; Wireless LAN; Analog-to-digital converter (ADC); SHA; current steering; data converter; delay-locked loop (DLL); digital-to-analog converter (DAC); flip-chip; high speed; pipeline; sample- and-hold; wireless LAN (WLAN);

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2006.875287

Filename

1661761