Title :
Zero waiting-cycle hierarchical block matching algorithm and its array architectures
Author :
Wang, Bor-Min ; Yen, Jui-Cheng ; Chang, Shyang
Author_Institution :
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
fDate :
2/1/1994 12:00:00 AM
Abstract :
A new hierarchical block matching algorithm with a novel arrangement of data flow is proposed. Its speed can be as fast as that of the conventional hierarchical block matching algorithms and its prediction quality is very close to the full search algorithm. In order to implement this algorithm, a multiprocessor array architecture for real-time processing is proposed. Due to the novel arrangement of data flow, the limitations of conventional ones will no longer exist. Moreover, the hardware complexity, size of local memory, input bandwidth, and speed performance of the proposed architecture are also analyzed. Finally, the simulation results are given to demonstrate the effectiveness of this new algorithm
Keywords :
CMOS integrated circuits; VLSI; block codes; digital signal processing chips; filtering and prediction theory; image coding; image sequences; motion estimation; parallel algorithms; real-time systems; systolic arrays; video signals; array architectures; data flow; hardware complexity; input bandwidth; local memory; multiprocessor array architecture; prediction quality; real-time processing; speed performance; zero waiting-cycle hierarchical block matching algorithm; Bandwidth; Computational complexity; Hardware; ISDN; Image coding; Motion estimation; Performance analysis; Prediction algorithms; Systolic arrays; Very large scale integration;
Journal_Title :
Circuits and Systems for Video Technology, IEEE Transactions on
