Title :
Bubble domain memory chips
Author_Institution :
IBM Thomas J. Watson Research Center, Yorktown Heights, N.Y.
fDate :
9/1/1972 12:00:00 AM
Abstract :
Three memory chip organizations (major/minor loops, decoders, and dynamically ordered shift registers) are described and assessed in terms of memory performance objectives.
Keywords :
Magnetic bubble logic circuits; Magnetic bubble memories; Shift registers; Assembly; Chip scale packaging; Circuits; Conductors; Decoding; Lattices; Lithography; Magnetic devices; Physics; Shift registers;
Journal_Title :
Magnetics, IEEE Transactions on
DOI :
10.1109/TMAG.1972.1067453
