Author :
Kawahara, Takayuki ; Takemura, Riichiro ; Miura, Katsuya ; Hayakawa, Jun ; Ikeda, Shoji ; Lee, Young Min ; Sasaki, Ryutaro ; Goto, Yasushi ; Ito, Kenchi ; Meguro, Toshiyasu ; Matsukura, Fumihiro ; Takahashi, Hiromasa ; Matsuoka, Hideyuki ; Ohno, Hideo
Abstract :
A 1.8 V 2 Mb SPin-transfer torque RAM (SPRAM) chip using a 0.2 mum logic process with an MgO tunneling barrier cell demonstrates the circuit technologies for potential low-power nonvolatile RAM, or universal memory. This chip features an array scheme with bit-by-bit bi-directional current writing to achieve proper spin-transfer torque writing of 100 ns, and parallelizing-direction current reading with a low-voltage bit-line for preventing read disturbances that lead to 40 ns access time.
Keywords :
CMOS memory circuits; low-power electronics; random-access storage; tunnelling magnetoresistance; SPRAM chip; bit-by-bit bi-directional current writing; low-power nonvolatile RAM; low-voltage bit-line; parallelizing-direction current reading; spin-transfer torque RAM; storage capacity 2 Mbit; tunneling barrier cell; universal memory; voltage 1.8 V; Bidirectional control; Circuits; Indium tin oxide; Laboratories; Nonvolatile memory; Random access memory; Read-write memory; Torque; Tunneling; Writing; Bi-directional current write parallelizing direction current read; TMR; low-power RAM; nonvolatile RAM; spin-transfer torque; universal memory;
