A Programmable 512 GOPS Stream Processor for Signal, Image, and Video Processing

Author

Khailany, Brucek K. ; Williams, Ted ; Lin, Jim ; Long, Eileen Peters ; Rygh, Mark ; Tovey, DeForest W. ; Dally, William J.

Author_Institution

Stream Processors Inc., Sunnyvale

Volume

43

Issue

1

fYear

2008

Firstpage

202

Lastpage

213

Abstract

A 34-million transistor stream processor system-on-chip (SoC) for signal, image, and video processing contains 80 parallel integer ALUs organized into 16 data-parallel lanes with a 5-ALU VLIW per lane, two CPU cores, and I/Os. Implemented in a 0.13 mum CMOS technology, sixteen 800 MHz data-parallel lanes combine to deliver performance of 512 8-bit GOPS or 256 16-bit GOPS, or 128 billion 16-bit multiply-accumulates per second GMACs), with a power efficiency of 82 pJ/MAC.

Keywords

digital signal processing chips; signal resolution; system-on-chip; video signal processing; CMOS technology; digital signal processor; image processing; programmable stream processor; signal processing; size 0.13 micron; transistor stream processor system-on-chip; video encoding; video processing; word length 16 bit; word length 8 bit; CMOS technology; Clocks; Digital signal processing; Image coding; Parallel processing; Signal processing; Streaming media; System-on-a-chip; Throughput; VLIW; Digital signal processor (DSP); H.264; stream processing; video encoding;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2007.909331

Filename

4443192