Analysis of the Impact of High-Order Integrator Dynamics on SC Sigma-Delta Modulator Performances

Author

Pugliese, Andrea ; Amoroso, Francesco Antonio ; Cappuccino, Gregorio ; Cocorullo, Giuseppe

Author_Institution

Dept. of Electron., Comput. Sci. & Syst., Univ. of Calabria, Cosenza, Italy

Volume

57

Issue

3

fYear

2010

fDate

3/1/2010 12:00:00 AM

Firstpage

618

Lastpage

630

Abstract

The impact of high-order integrator dynamics on switched-capacitor sigma-delta modulator (????M) performances is investigated in this paper. An advanced generic integrator-settling model to take into account high-order dynamic effects is presented and validated by means of transistor-level simulations of circuits implemented in a commercial 0.35 ??m CMOS technology. The model is used through the paper to carry out an exhaustive behavioral analysis for second-order single-bit ????Ms characterized by first-, second-, and third-order integrator dynamics, showing how high-order poles and zeros can affect the ????M characteristics remarkably. The proposed analysis provides useful guidelines to fix a convenient integrator poles/zeros placement in order to achieve an effective ????M design flow.

Keywords

CMOS integrated circuits; integrating circuits; poles and zeros; sigma-delta modulation; switched capacitor networks; ????M; CMOS technology; behavioral modeling; generic integrator-settling model; high-order integrator dynamics; poles and zeros; size 0.35 mum; switched-capacitor sigma-delta modulator; transistor-level simulations; Behavioral modeling; operational amplifier (op-amp); settling time; sigma-delta modulator $(SigmaDelta {rm Ms})$; switched-capacitor (SC) integrator; transient response;

fLanguage

English

Journal_Title

Circuits and Systems I: Regular Papers, IEEE Transactions on

Publisher

ieee

ISSN

1549-8328

Type

jour

DOI

10.1109/TCSI.2009.2023946

Filename

5061571