Title :
Algorithmic design of a hierarchical and modular leading zero detector circuit
Author :
Oklobdzija, V.G.
Author_Institution :
California Univ., Davis, CA, USA
Abstract :
A novel way of implementing the leading zero detector (LZD) circuit is described. The implementation is based on an algorithmic approach resulting in a modular and scalable circuit for any number of bits. This approach to LZD design yields both speed and area advantages over logic synthesis.
Keywords :
CMOS integrated circuits; digital arithmetic; logic CAD; CMOS; LZD design; algorithmic approach; algorithmic design; any number of bits; area advantages; hierarchical circuit; implementation; leading zero detector circuit; modular circuit; scalable circuit; speed advantage;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19930193
