• DocumentCode
    1051134
  • Title

    Architectures for finite radon transform

  • Author

    Rahman, C.A. ; Badawy, W.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Univ. of Calgary, Alta., Canada
  • Volume
    40
  • Issue
    15
  • fYear
    2004
  • fDate
    7/22/2004 12:00:00 AM
  • Firstpage
    931
  • Lastpage
    932
  • Abstract
    Two VLSI architectures for the finite Radon transform are presented. The first is a reference architecture using memory blocks and the second is a memoryless architecture. The proposed architectures use 7×7 size image blocks and are prototyped for processing the CIF image sequence. The simulation and synthesis results show that the core speeds of the two proposed architectures are around 100 and 82 MHz, respectively.
  • Keywords
    Radon transforms; VLSI; image sequences; integrated logic circuits; memoryless systems; parallel architectures; 100 MHz; 82 MHz; CIF image sequence processing; VLSI architectures; finite Radon transform; image blocks; image resolution; memory blocks; memoryless architecture; reference architecture;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:20040566
  • Filename
    1318875
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1051134