• DocumentCode
    1051238
  • Title

    Floating CMOS resistor

  • Author

    Wilson, G. ; Chan, P.K.

  • Author_Institution
    Plymouth Univ., UK
  • Volume
    29
  • Issue
    3
  • fYear
    1993
  • Firstpage
    306
  • Lastpage
    307
  • Abstract
    A floating resistor scheme is described in which a CMOS device is linearised by the application of a suitably scaled common-mode signal to the gate terminal only. SPICE studies indicate that the proposed resistor offers low distortion over a tuning range of 3:1. The design, for which a patent application has been filed, makes no special demands on device aspect ratios and could offer an economic alternative to fully-balanced topologies.
  • Keywords
    CMOS integrated circuits; SPICE; circuit analysis computing; resistors; CMOS device; SPICE studies; aspect ratios; floating resistor scheme; gate terminal; scaled common-mode signal; tuning range;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19930209
  • Filename
    277189
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1051238