Title :
A Digital 1.6 pJ/bit Chip Identification Circuit Using Process Variations
Author :
Su, Ying ; Holleman, Jeremy ; Otis, Brian P.
Author_Institution :
Washington Univ., Seattle
Abstract :
A 128-bit, 1.6 pJ/bit, 96% stable chip ID generation circuit utilizing process variations is designed in a 0.13 mum CMOS process. The circuit consumes 162 nW from a 1 V supply at low readout frequencies and 1.6 muW at 1 Mb/s. Cross-coupled logic gates were employed to simultaneously generate, amplify, and digitize the random circuit offset to create a stable unique digital chip ID code. A thorough statistical analysis is presented in order to explore the ID circuit reliability and stability. Two ID generators with different layout techniques were designed and fabricated to provide a performance comparison of power consumption, ID stability, and ID statistical robustness.
Keywords :
CMOS logic circuits; integrated circuit reliability; low-power electronics; radiofrequency identification; statistical analysis; CMOS process; ID circuit reliability; ID stability; ID statistical robustness; RFID; bit rate 1 Mbit/s; cross-coupled logic gates; digital chip ID code; digital chip identification circuit; layout techniques; low-power digital electronics; power 162 nW; power consumption; process variations; sensor networks; size 0.13 micron; stable chip ID generation circuit; statistical analysis; word length 128 bit; CMOS logic circuits; CMOS process; Circuit stability; Frequency; Logic circuits; Logic gates; Process design; Robust stability; Stability analysis; Statistical analysis; Chip identification; RFID; low-power digital electronics; mismatch; process variations; sensor networks;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2007.910961
