Author :
Wang, Yih ; Ahn, Hong Jo ; Bhattacharya, Uddalak ; Chen, Zhanping ; Coan, Tom ; Hamzaoglu, Fatih ; Hafez, Walid M. ; Jan, Chia-Hong ; Kolar, Pramod ; Kulkarni, Sarvesh H. ; Lin, Jie-Feng ; Ng, Yong-Gee ; Post, Ian ; Wei, Liqiong ; Zhang, Ying ; Zhang, Kev
Abstract :
A low-power, high-speed SRAM macro is designed in a 65 nm ultra-low-power (ULP) logic technology for mobile applications. The 65 nm strained silicon technology improves transistor performance/leakage tradeoff, which is essential to achieve fast SRAM access speed at substantially low operating voltage and standby leakage. The 1 Mb SRAM macro features a 0.667 mum2 low-leakage memory cell and can operate over a wide range of supply voltages from 1.2 V to 0.5 V. It achieves operating frequency of 1.1 GHz and 250 MHz at 1.2 V and 0.7 V, respectively. The SRAM leakage is reduced to 12 muA/Mb at the data retention voltage of 0.5 V. The measured bitcell leakage from the SRAM array is ~2 pA/bit at retention voltage with integrated leakage reduction schemes.
Keywords :
CMOS memory circuits; SRAM chips; low-power electronics; SRAM design; frequency 1.1 GHz; frequency 250 MHz; integrated leakage reduction schemes; low-leakage memory cell; mobile application; size 65 nm; strained silicon technology; transistor leakage; transistor performance; ultra-low-power CMOS technology; voltage 1.2 V to 0.5 V; CMOS logic circuits; CMOS technology; Central Processing Unit; Costs; Energy consumption; Integrated circuit technology; Logic design; Random access memory; Silicon; Voltage; Low-power memory; MOS memory integrated circuits; sleep transistor; static random-access memory (SRAM);
