• DocumentCode
    1052069
  • Title

    Reliability, reconfiguration, and spare allocation issues in binary-tree architectures based on multiple-level redundancy

  • Author

    Chen, Yung-Yuan ; Upadhyaya, Shambhu J.

  • Author_Institution
    Chung-Hua Polytech. Inst., Hsinchu, Taiwan
  • Volume
    42
  • Issue
    6
  • fYear
    1993
  • fDate
    6/1/1993 12:00:00 AM
  • Firstpage
    713
  • Lastpage
    723
  • Abstract
    The locally redundant modular tree (LRMT) schemes offer high yield and reliability for trees of relatively few levels but are less effective for large binary trees due to the imbalance of reliability of different levels. A new multiple-level redundancy tree (MLRT) architecture that combines modular schemes with level-oriented schemes which lead to better yield and reliability is presented. The MLRT structure enhances the wafer yield to significant levels by offering separate layers of protection for random and clustered defects. Unlike most existing techniques, this technique performs a more accurate reliability analysis by taking into account both switch and link failures. A measure called the marginal switch to processing element area ratio (MSR) is introduced to precisely characterize the effect of switch complexity on the reliability of the redundant system. A systematic method for the optimal distribution of spare modules of the MLRT structure is also presented. The analyses show that the MLRT structure offers higher yield and system reliability than LRMT and subtree-oriented fault-tolerance (SOFT) structures do
  • Keywords
    fault tolerant computing; parallel architectures; redundancy; MLRT; MSR; SOFT; binary-tree architectures; locally redundant modular tree; marginal switch to processing element area ratio; multiple-level redundancy; multiple-level redundancy tree; reliability; subtree-oriented fault-tolerance; switch complexity; system reliability; wafer yield; Area measurement; Binary trees; Failure analysis; Fault tolerance; Fault tolerant systems; Manufacturing processes; Performance analysis; Protection; Redundancy; Switches;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/12.277283
  • Filename
    277283