Asymmetry in Gate Capacitance–Voltage – Behavior of Ultrathin Metal Gate MOSFETs With Gate Dielect

Anomalous asymmetry (which here means "beyond that to be expected classically") between accumulation and strong inversion was observed in the measured capacitance-voltage (C-V) curves of metal gate nMOSFETs with ~ 1 nm equivalent oxide thickness (EOT) HfO₂ layers and was analyzed and extrapolated to still smaller devices and to pMOS devices using self-consistent Poisson-Schrodinger simulations. The experimental devices were fabricated via atomic layer deposition (ALD) of HfO₂ on stress-relieved preoxide (SRPO), followed by tantalum carbon alloy metal gate deposition. Simulations suggest two underlining mechanisms for this anomalous asymmetry, namely 1) differing degrees of quantum mechanical carrier penetration into the dielectric associated with the differing electron and hole barriers and 2) differing degrees of quantum confinement within the substrate, which result from differing electron and hole bandstructures in the Si. Both mechanisms result in greater capacitance when the quantum-confined surface carriers are electrons than when they are holes. Simulations indicate that this effect can produce asymmetries between pMOS and nMOS devices under strong inversion for the same physical gate stack that will become increasingly important as the trend toward smaller devices and use of high-kappa dielectrics continues: perhaps approximately 10% reduction in pMOS strong-inversion capacitance relative to that of nMOS devices for 0.5 nm EOT high-kappa gate stacks