• DocumentCode
    10526
  • Title

    Energy Efficient Group-Sort QRD Processor With On-Line Update for MIMO Channel Pre-Processing

  • Author

    Chenxin Zhang ; Prabhu, Hemanth ; Yangxurui Liu ; Liang Liu ; Edfors, Ove ; Owall, Viktor

  • Author_Institution
    Dept. of Electr. & Inf. Technol., Lund Univ., Lund, Sweden
  • Volume
    62
  • Issue
    5
  • fYear
    2015
  • fDate
    May-15
  • Firstpage
    1220
  • Lastpage
    1229
  • Abstract
    This paper presents a Sorted QR-Decomposition (SQRD) processor for 3GPP LTE-A system. It achieves energy-efficiency by co-optimizing techniques, such as heterogeneous processing, reconfigurable architecture, and dual-supply voltage operation. At algorithm level, a low-complexity hybrid decomposition scheme is adopted, which switches, depending on the energy distribution of spatial channels, between the traditional brute-force SQRD and a proposed group-sort QR-update strategy. A reconfigurable vector processor is accordingly developed to support the adaptive processing with high hardware efficiency. Furthermore, on-chip power management technique is also integrated to obtain real-time power-saving by adapting the voltage supply based on the instantaneous workload. As a proof-of-concept, we implemented the processor using a 65 nm CMOS technology and conducted post-layout simulation. The proposed SQRD processor occupies 0.71 mm2 core area and has a throughput of up to 69 MQRD/s. Compared to the brute-force approach, an energy reduction of 10 ~ 61.8% is achieved.
  • Keywords
    3G mobile communication; CMOS digital integrated circuits; Long Term Evolution; MIMO communication; computational complexity; energy conservation; matrix decomposition; microprocessor chips; 3GPP LTE-A system; CMOS technology; MIMO channel pre-processing; SQRD processor; adaptive processing; brute-force approach; co-optimizing technique; dual-supply voltage operation; energy reduction; energy-efficient group-sort QRD processor; group-sort QR-update strategy; hardware efficiency; heterogeneous processing; instantaneous workload; low-complexity hybrid decomposition scheme; on-chip power management technique; online update; post-layout simulation; real-time power-saving; reconfigurable vector processor; size 65 nm; sorted QR-decomposition processor; spatial channel energy distribution; traditional brute-force SQRD; Complexity theory; Computer architecture; Hardware; MIMO; Matrix decomposition; Sorting; Vectors; Channel pre-processing; MIMO; QR decomposition; reconfigurable processor; sorting;
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems I: Regular Papers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1549-8328
  • Type

    jour

  • DOI
    10.1109/TCSI.2015.2402936
  • Filename
    7076657