• DocumentCode
    1052749
  • Title

    Electrically alterable avalanche-injection-type MOS READ-ONLY memory with stacked-gate structure

  • Author

    Iizuka, Hisakazu ; Masuoka, Fujio ; Sato, Tai ; Ishikawa, Mistuaki

  • Author_Institution
    Toshiba Electric Co., Ltd., Kawasaki, Kanagawa, Japan
  • Volume
    23
  • Issue
    4
  • fYear
    1976
  • fDate
    4/1/1976 12:00:00 AM
  • Firstpage
    379
  • Lastpage
    387
  • Abstract
    Design theory and experimental results of the WRITE and ERASE properties of a rewritable and nonvolatile avalanche-injection-type memory are reported. The memory transistor has the stacked-gate structure of a floating gate and a control gate. The threshold-voltage shift of the transistor due to injected charge is controlled by applied potential on the control gate which reduces the avalanche breakdown voltage of the drain junction and accelerates electron injection into the floating gate. The writing time is about 20 µs for a single transistor and is less than 5 s for a fully decoded 2048-bit memory with appropriate duty cycles of programming pulses. Erasure of the memory is accomplished either by ultraviolet light irradiation onto the floating gate or by electric field emission of electrons from the floating gate to the control gate. Electrical erasing is theoretically analyzed and successfully compared with experimental results on the 2K bit memory. Memory retention is also investigated and a charge-escaping model is proposed.
  • Keywords
    Acceleration; Avalanche breakdown; Breakdown voltage; Decoding; Electron emission; Lighting control; Nonvolatile memory; Threshold voltage; Voltage control; Writing;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/T-ED.1976.18415
  • Filename
    1478429