Title :
An asymmetric sidewall process for high performance LDD MOSFET´s
Author :
Horiuchi, Tadahiko ; Homma, Tetsuya ; Murao, Yukinobu ; Okumura, Koichiro
Author_Institution :
ULSI Device Dev. Lab., NEC Corp., Sagamihara, Japan
fDate :
2/1/1994 12:00:00 AM
Abstract :
An asymmetric LDD sidewall spacer technology is presented which gives a high drivability of LDD MOSFET without sacrificing hot carrier immunity. The asymmetric spacer is fabricated by using a selective oxide deposition technique. The process implemented in a CMOS fabrication sequence requires no additional masking step. The fact that no reliability problems are introduced in the transistor characteristics by the selective oxide deposition process is also examined
Keywords :
CMOS integrated circuits; hot carriers; insulated gate field effect transistors; ion implantation; oxidation; reliability; CMOS fabrication sequence; LDD MOSFET; LDD ion implant; asymmetric LDD sidewall spacer technology; drain current characteristics; high drivability; hot carrier immunity; parasitic resistance; reliability; selective oxide deposition technique; CMOS process; CMOS technology; Circuit optimization; Fabrication; Hot carriers; Implants; MOSFET circuits; Negative feedback; Space technology; Voltage;
Journal_Title :
Electron Devices, IEEE Transactions on
