A Power Optimized Continuous-Time ∆Σ ADC for Audio Applications

Author

Pavan, Shanthi ; Krishnapura, Nagendra ; Pandarinathan, Ramalingam ; Sankar, Prabu

Author_Institution

Indian Inst. of Technol., Madras

Volume

43

Issue

2

fYear

2008

Firstpage

351

Lastpage

360

Abstract

We present design considerations for low-power continuous-time modulators. Circuit design details and measurement results for a 15 bit audio modulator are given. The converter, designed in a 0.18 mum CMOS technology, achieves a dynamic range of 93.5 dB in a 24 kHz bandwidth and dissipates 90 muW from a 1.8 V supply. It features a third-order active-RC loop filter, a very low-power 4-bit flash quantizer, and an efficient excess-delay compensation scheme to reduce power dissipation.

Keywords

CMOS integrated circuits; RC circuits; audio equipment; compensation; continuous time filters; delays; integrated circuit design; low-power electronics; sigma-delta modulation; 4-bit flash quantizer; CMOS technology; audio modulator; bandwidth 24 kHz; circuit design; continuous-time DeltaSigma ADC; converter; excess-delay compensation scheme; power 90 muW; size 0.18 mum; third-order active-RC loop filter; voltage 1.8 V; word length 15 bit; Analog-digital conversion; Bandwidth; CMOS technology; Circuit noise; Circuit synthesis; Dynamic range; Filters; Noise reduction; Power dissipation; Quantization; Analog-to-digital converter (ADC); continuous time; data converter; jitter; oversampling; sigma-delta modulation;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2007.914263

Filename

4444576