Real-time realisation of noise-immune gradient-based edge detector

A computational field-programmable gate array (FPGA) realisation for edge detection that is particularly immune to noise by a digital approximated Gaussian smoothing filter is described. The proposed systolic array architecture was examined for convolution operation in order to put simplicity and regularity to the design. Moreover, most of the presented processing structures are highly pipelined, so that the goal of real-time computing is substantially achieved with the processing frame rate reaching up to 280 frames per second. For an efficient hardware mapping, the absolute difference mask algorithm was adopted because of its regularity and independent operations, as well as its important property of performing one-pixel-edge localisation. A scalable first in, first out (FIFO) design was also proposed to make the edge detector applicable to five different image sizes. The FPGA realisation on the presented versatile development platform shows that the proposed design improves both the speed and the hardware usage. This is attributed to the utilisation of the proposed parallel and pipelined structure so that a fast operating speed of 73.6 MHz, which is about 265 times faster than the digital signal processing environment, is obtained in the present investigation.