DocumentCode :
1053482
Title :
Fast-Lock Hybrid PLL Combining Fractional- N and Integer-N Modes of Differing Bandwidths
Author :
Woo, Kyoungho ; Liu, Yong ; Nam, Eunsoo ; Ham, Donhee
Author_Institution :
Harvard Univ., Cambridge
Volume :
43
Issue :
2
fYear :
2008
Firstpage :
379
Lastpage :
389
Abstract :
We introduce a single-loop PLL that operates in a narrower-bandwidth, integer-N mode during phase lock and in a wider-bandwidth, fractional-N mode during transient. This hybrid PLL, as a generalization of the conventional variable-bandwidth PLL that shifts only its bandwidth, simultaneously achieves the fast-locking advantage of the fractional-N PLL and design simplicity of the integer-N PLL, and as such, brings benefits in certain important PLL applications. In addition, the frequency division mode switching, unique in the hybrid PLL, enables a new, more digital protocol to execute bandwidth switching. A CMOS IC prototype attests to the validity of the proposed approach.
Keywords :
CMOS integrated circuits; phase locked loops; CMOS IC; bandwidth switching; digital protocol; fast-lock hybrid PLL; fractional-N PLL; integer-N mode PLL; phase locked loop; Bandwidth; CMOS integrated circuits; Frequency conversion; Frequency synthesizers; Laser mode locking; Phase locked loops; Phase noise; Protocols; Steady-state; Voltage-controlled oscillators; Charge-pump phase-locked loops; fractional-$N$ frequency synthesizers; integer-$N$ frequency synthesizers; phase-locked loops;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.2007.914281
Filename :
4444584
Link To Document :
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