DocumentCode :
1053678
Title :
Modeling and simulation of the SDC data collection chip
Author :
Hughes, E. ; Tharakan, G. ; Downing, R. ; Haney, M. ; Golin, E. ; Jones, L. ; Knapp, D. ; Thaler, J.
Author_Institution :
Illinois Univ., Urbana, IL, USA
Volume :
39
Issue :
2
fYear :
1992
fDate :
4/1/1992 12:00:00 AM
Firstpage :
130
Lastpage :
137
Abstract :
A description is presented of modeling and simulation of the data collection chip (DCC) design for the Solenoidal Detector Collaboration (SDC). Models of the DCC written in Verilog and VHDL are described, and results are presented. The models have been simulated to study queue depth requirements and to compare control feedback alternatives. Insight into the management of models and simulation tools is given. Finally, techniques useful in the design process for data acquisition systems are discussed
Keywords :
circuit analysis computing; computerised control; data acquisition; digital signal processing chips; digital simulation; feedback; nuclear electronics; physical instrumentation control; physics computing; DCC; SDC data collection chip; Solenoidal Detector Collaboration; VHDL; Verilog; control feedback alternatives; data acquisition systems; design process; modeling; queue depth requirements; simulation; Circuit simulation; Computer languages; Data acquisition; Detectors; Hardware design languages; Mesons; Power system modeling; Stochastic systems; USA Councils; Very high speed integrated circuits;
fLanguage :
English
Journal_Title :
Nuclear Science, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9499
Type :
jour
DOI :
10.1109/23.277472
Filename :
277472
Link To Document :
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