Optimum design of thyristor gate—Emitter geometry

This paper describes a new method of studying the influence of the gate-emitter geometrical configuration of thyristors upon their triggering performances. This method allows, for devices of any geometrical complexity, to calculate the emitter bias voltage distribution prior to turn-on and hence to compare the behavior of these devices from a geometrical point of view. The results may be used as guide lines for the optimum design of gate-emitter configurations. As examples, precise design rules are given for standard thyristors and application to amplifying interdigited gate thyristors are outlined.