A Magnetic Feedback Method for Low-Voltage CMOS LNA Reverse-Isolation Enhancement

A magnetic feedback method for enhancing the reverse isolation of low-voltage (1.2-V), single-transistor CMOS low-noise amplifiers (LNAs) is presented. The method neutralizes the gate-drain overlap capacitance of the amplifying transistor, allowing for adequate reverse isolation without gain reduction. The method does not require a differential LNA topology and input matching is facilitated since the degeneration inductor is not a part of a magnetic feedback loop. In addition, it allows for neutralizing the intrinsic part of the parasitic capacitance, which cannot be neglected in short-channel devices. Simulation results utilizing a standard 0.18-m CMOS process indicate a 17-29-dB improvement in the reverse-isolation performance with minimal noise figure deterioration.