• DocumentCode
    1054765
  • Title

    Formal verification of sequential hardware: a tutorial

  • Author

    McFarland, Michael C.

  • Author_Institution
    Dept. of Comput. Sci., Boston Coll., Chestnut Hill, MA, USA
  • Volume
    12
  • Issue
    5
  • fYear
    1993
  • fDate
    5/1/1993 12:00:00 AM
  • Firstpage
    633
  • Lastpage
    654
  • Abstract
    Various formal verification techniques and how they can be applied to sequential hardware, especially at the register-transfer level, are examined. The basic elements of a verification system, as illustrated on the relatively simple problem of verifying combinational circuits, are presented. The more complex problems involved in analyzing sequential systems and the techniques that have been developed to solve them are then considered. Throughout, the focus is on those techniques whose utility has been demonstrated on real systems, including higher order logic, temporal logic, predicate transformers, state-machine models, and model checkers
  • Keywords
    logic CAD; sequential circuits; sequential machines; sequential switching; switching theory; formal verification techniques; higher order logic; model checkers; predicate transformers; register-transfer level; sequential hardware; state-machine models; temporal logic; Combinational circuits; Computational modeling; Digital systems; Formal verification; Hardware; Logic circuits; Logic design; Testing; Transformers; Tutorial;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.277609
  • Filename
    277609