VLSI implementation of inverse discrete cosine transformer and motion compensator for MPEG2 HDTV video decoding

Author

Masaki, Toshihiro ; Morimoto, Yasuo ; Onoye, Takao ; Shirakawa, Isao

Author_Institution

Dept. of Inf. Syst. Eng., Osaka Univ., Japan

Volume

5

Issue

5

fYear

1995

fDate

10/1/1995 12:00:00 AM

Firstpage

387

Lastpage

395

Abstract

An MPEG2 video decoder core dedicated to MP@HL (Main Profile at High Level) images is described with the main theme focused on an inverse discrete cosine transformer and a motion compensator. By means of various novel architectures, the inverse discrete cosine transformer achieves a high throughput, and the motion compensator performs different types of picture prediction modes employed by the MPEG2 algorithm. The decoder core, implemented in the total chip area of 22.0 mm² by a 0.6-μm triple-metal CMOS technology, processes a macroblock within 3.84 μs, and therefore is capable of decoding HDTV (1920×1152 pels) images in real time

Keywords

CMOS digital integrated circuits; VLSI; code standards; decoding; discrete cosine transforms; high definition television; inverse problems; motion compensation; telecommunication standards; video signal processing; 0.6 micron; 1152 pixel; 1920 pixel; 2211840 pixel; HDTV images; MPEG2 HDTV video decoding; MPEG2 algorithm; MPEG2 video decoder; Main Profile at High Level; VLSI; high throughput; inverse discrete cosine transformer; macroblock; motion compensator; picture prediction modes; real time decoding; triple-metal CMOS technology; Asynchronous transfer mode; CMOS technology; Decoding; HDTV; Image coding; Image storage; Transformer cores; Very large scale integration; Video compression; Videoconference;

fLanguage

English

Journal_Title

Circuits and Systems for Video Technology, IEEE Transactions on

Publisher

ieee

ISSN

1051-8215

Type

jour

DOI

10.1109/76.473552

Filename

473552