A novel modular systolic array architecture for full-search block matching motion estimation

Author

Yee, H. ; Hu, Yu Hen

Author_Institution

Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA

Volume

5

Issue

5

fYear

1995

fDate

10/1/1995 12:00:00 AM

Firstpage

407

Lastpage

416

Abstract

A novel modular systolic array architecture for the full search block matching motion estimation algorithm (FBMA) is presented. The design efforts are focused on matching the array computation to system level input/output constraints. Compared to previously proposed FBMA architectures, this new architecture delivers highest throughput rate, achieves 100% processor utilization, requires much fewer input/output lines (pin count), and is linearly scalable. As such, this architecture offers a feasible solution for progressive-scan HDTV picture format

Keywords

high definition television; image matching; modules; motion estimation; search problems; systolic arrays; array computation; full-search block matching motion estimation; linearly scalable architecture; modular systolic array architecture; pin count; progressive-scan HDTV picture format; system level input/output constraints; throughput rate; Bandwidth; Computer architecture; HDTV; Information technology; Merging; Motion estimation; Systolic arrays; Throughput; Very large scale integration; Video compression;

fLanguage

English

Journal_Title

Circuits and Systems for Video Technology, IEEE Transactions on

Publisher

ieee

ISSN

1051-8215

Type

jour

DOI

10.1109/76.473553

Filename

473553