A 65 nm 2-Billion Transistor Quad-Core Itanium Processor

Author

Stackhouse, Blaine ; Bhimji, Sal ; Bostak, Chris ; Bradley, Dave ; Cherkauer, Brian ; Desai, Jayen ; Francom, Erin ; Gowan, Mike ; Gronowski, Paul ; Krueger, Dan ; Morganti, Charles ; Troyer, Steve

Author_Institution

Intel Corp., Fort Collins, CO

Volume

44

Issue

1

fYear

2009

Firstpage

18

Lastpage

31

Abstract

This paper describes an Itanium processor implemented in 65 nm process with 8 layers of Cu interconnect. The 21.5 mm by 32.5 mm die has 2.05B transistors. The processor has four dual-threaded cores, 30 MB of cache, and a system interface that operates at 2.4 GHz at 105degC . High speed serial interconnects allow for peak processor-to-processor bandwidth of 96 GB/s and peak memory bandwidth of 34 GB/s.

Keywords

UHF integrated circuits; cache storage; copper; integrated circuit interconnections; microprocessor chips; multiprocessor interconnection networks; nanoelectronics; 2-billion transistor quad-core Itanium processor; 2.05 billion transistors; 30 MB cache; Cu; dual-threaded cores; frequency 2.4 GHz; high-speed serial interconnects; peak memory bandwidth; processor-to-processor bandwidth; size 65 nm; storage capacity 30 Mbit; system interface; temperature 105 degC; Bandwidth; Circuit synthesis; Clocks; Communication system control; Copper; Integrated circuit interconnections; Microprocessors; Packaging; Transistors; Voltage; 65-nm process technology; circuit design; clock distribution; computer architecture; microprocessor; on-die cache; voltage domains;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2008.2007150

Filename

4735536