DocumentCode
1055035
Title
2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology
Author
Somasekhar, Dinesh ; Yibin Ye ; Aseron, Paolo ; Lu, Shih-Lien ; Khellah, Muhammad M. ; Howard, Jason ; Ruhl, Greg ; Karnik, Tanay ; Borkar, Shekhar ; De, Vivek K. ; Keshavarzi, Ali
Author_Institution
Circuit Res. Labs., Intel Corp., Hillsboro, OR
Volume
44
Issue
1
fYear
2009
Firstpage
174
Lastpage
185
Abstract
We present 2 Mb 2T PMOS gain cell macro on 65 nm logic process that has high bandwidth of 128 GBytes/sec, fast cycle time of 2 ns and 6-clock cycles access time at 2 GHz. Macro features a full-rate pipelined architecture, ground precharge bitline, non-destructive read-out, partial write support and 128-row refresh to tolerate short refresh time. Cell is 2X denser than SRAM and is voltage compatible with logic.
Keywords
DRAM chips; logic design; logic devices; pipeline processing; 2T gain cell memory macro; byte rate 128 GByte/s; eDRAM cells; frequency 2 MHz; ground precharge bitline; logic process technology; non-destructive read-out; partial write support; pipelined architecture; size 65 nm; Bandwidth; Circuits; Clocks; Costs; Engines; Ground support; Logic; Microprocessors; Random access memory; Voltage; 2T cell; 3T cell; Bandwidth; dram; eDRAM; gain cell; memory;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.2008.2007155
Filename
4735548
Link To Document