A compact real-time vision system using integrated memory array processor architecture

Author

Okazaki, Shin Ichiro ; Fujita, Yoshihiro ; Yamashita, Nobuyuki

Author_Institution

Inf. Technol. Res. Labs., NEC Corp., Kanagawa, Japan

Volume

5

Issue

5

fYear

1995

fDate

10/1/1995 12:00:00 AM

Firstpage

446

Lastpage

452

Abstract

This paper describes the real-time vision system (RVS-2) which shows quite high performance for low-level image processing while it is implemented in a one-board type compact size format with small power consumption. The RVS-2 consists of an IMAP board, a video board and a host workstation. The IMAP board consists of eight highly-integrated IMAP LSIs and a dedicated control LSI (RVSC). The IMAP chip integrates 2 Mb image memory and 64 processing elements that operate in the SIMD mode. The RVSC chip performs global data operations efficiently without interactions with the host workstation, as well providing an instruction stream to the IMAP chips. The peak performance of the RVS-2 is 30 GIPS and most of the basic image processing tasks are carried out within about 0.1-0.7 ms, which is about 50-300 times faster than the video frame rate

Keywords

digital signal processing chips; image processing; integrated memory circuits; large scale integration; parallel architectures; real-time systems; 2 Mbyte; IMAP LSI; IMAP board; RVS-2; RVSC chip; SIMD mode; dedicated control LSI; global data operations; host workstation; image memory; image processing; integrated memory array processor architecture; low-level image processing; processing elements; real-time vision system; video board; Energy consumption; Image processing; Large scale integration; Machine vision; Memory architecture; Optical computing; Pixel; Real time systems; Sensor phenomena and characterization; Streaming media;

fLanguage

English

Journal_Title

Circuits and Systems for Video Technology, IEEE Transactions on

Publisher

ieee

ISSN

1051-8215

Type

jour

DOI

10.1109/76.473557

Filename

473557