DocumentCode
1055832
Title
Frequency granularity in digital phaselock loops
Author
Gardner, Floyd M.
Author_Institution
Gardner Res. Co., Palo Alto, CA, USA
Volume
44
Issue
6
fYear
1996
fDate
6/1/1996 12:00:00 AM
Firstpage
749
Lastpage
758
Abstract
The frequency of a digital phaselock loop (DPLL) is necessarily quantized. Feedback around the quantizing nonlinearity leads to a steady-state limit cycle. Properties of the limit cycle were obtained by computer simulation, and are reported here. Empirical formulas for guidance in DPLL design were developed
Keywords
circuit analysis computing; digital phase locked loops; feedback; limit cycles; quantisation (signal); DPLL design; computer simulation; digital phaselock loops; feedback; frequency granularity; quantizing nonlinearity; steady-state limit cycle; Feedback loop; Frequency synchronization; Jitter; Limit-cycles; Modems; Noise level; Phase noise; Quantization; Registers; Voltage-controlled oscillators;
fLanguage
English
Journal_Title
Communications, IEEE Transactions on
Publisher
ieee
ISSN
0090-6778
Type
jour
DOI
10.1109/26.506392
Filename
506392
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