Title :
A Passive Switched-Capacitor Finite-Impulse-Response Equalizer
Author :
Guilar, N.J. ; Lau, F. ; Hurst, P.J. ; Lewis, S.H.
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Davis, CA
Abstract :
A passive CMOS switched-capacitor finite-impulse-response equalizer is described. A sampling rate of 200 MS/s is achieved by six time-interleaved channels. Nonlinear parasitic capacitance scales the equalized output but does not affect the zero locations of the equalizer for a binary or ternary data signal. The 4-tap equalizer prototype is fully differential. At 200 MS/s, the equalizer dissipates 19.5 mW, which is virtually all consumed by clock drivers, and occupies an active area of 1.3 mm2 in a 0.35 mum CMOS process
Keywords :
CMOS integrated circuits; FIR filters; equalisers; switched capacitor filters; telecommunication channels; 0.35 micron; 19.5 mW; 4-tap equalizer prototype; CMOS process; FIR filter; binary data signal; clock drivers; nonlinear parasitic capacitance; passive switched-capacitor finite-impulse-response equalizer; six time-interleaved channels; switched-capacitor filter; ternary data signal; Circuits; Clocks; Communication channels; Digital filters; Equalizers; Finite impulse response filter; Intersymbol interference; Parasitic capacitance; Prototypes; Sampling methods; Equalizer; FIR filter; switched-capacitor filter;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2006.889378
