Abstract :
In this paper, we proposed a new architecture of lifting processor for JPEG2000 and implemented it with both FPGA and ASIC. It includes a new cell structure that executes a unit of lifting calculation to satisfy the requirements of the lifting process of a repetitive arithmetic. After analyzing the operational sequence of lifting arithmetic in detail and imposing the causality to implement in hardware, the unit cell was optimized. A new simple lifting kernel was organized by repeatedly arranging the unit cells and a lifting processor was realized for Motion JPEG2000 with the kernel. The proposed processor can handle any size of tiles and support both lossy and lossless operation with (9,7) filter and (5,3) filter, respectively. Also, it has the same throughput rate as the input, and can continuously output the wavelet coefficients of the four types (LL, LH, HL, HH) simultaneously. The lifting processor was implemented in a 0.35 mum CMOS fabrication process, the result of which occupied about 90 000 gates, and was stably operated in about 150 MHz
Keywords :
VLSI; application specific integrated circuits; discrete wavelet transforms; field programmable gate arrays; image processing; 0.35 micron; ASIC; FPGA; VLSI architecture; discrete wavelet transform; lifting calculation; lifting process; line-based lifting wavelet transform; motion JPEG2000; Application specific integrated circuits; Field programmable gate arrays; Filters; Hardware; Throughput; Very large scale integration; Wavelet transforms; ASIC; FPGA; VLSI; discrete wavelet transform (DWT); factorization; lifting;
