Title :
Multiple fault detection in fan-out free circuits using minimal single fault test set
Author :
Lai, K. ; Lala, P.K.
Author_Institution :
Dept. of Electr. Eng., North Carolina A&T State Univ., Greensboro, NC, USA
fDate :
6/1/1996 12:00:00 AM
Abstract :
This paper presents a new algorithm to generate test sets for single stuck-at faults, which also detect all multiple stuck-at faults in fan-out-free circuits. This algorithm derives the test set for each node in a fan-out-free circuit by calculating the output count of the node. The output count indicates the number of test patterns needed to check for all faults in the corresponding subcircuit. The fan-out-free circuit can be any combination of AND, OR, NOT, NAND, and NOR gates
Keywords :
VLSI; combinational circuits; fault diagnosis; integrated circuit testing; logic testing; VLSI devices; fan-out free circuits; logic circuits; minimal single fault test set; multiple fault detection; output count; single stuck-at faults; single-fault assumption; test generation; Circuit faults; Circuit testing; Combinational circuits; Costs; Delay; Electrical fault detection; Fault detection; Logic circuits; Logic testing; Very large scale integration;
Journal_Title :
Computers, IEEE Transactions on
