DocumentCode
1056497
Title
High sample rate array architectures for median filters
Author
Chakrabarti, Chaitali
Author_Institution
Dept. of Electr. Eng., Arizona State Univ., Tempe, AZ, USA
Volume
42
Issue
3
fYear
1994
fDate
3/1/1994 12:00:00 AM
Firstpage
707
Lastpage
712
Abstract
Presents high sample rate semi-systolic array architectures for computing 1D and 2D nonrecursive and recursive median filters. A high sample rate is obtained by pipelining the computations in each processor. Although the nonrecursive filters are pipelined by placing latches in the feedforward paths, the recursive filters are restructured to create additional delays in the feedback paths, and then pipelined using the delays as latches
Keywords
delays; digital filters; pipeline processing; systolic arrays; two-dimensional digital filters; 1D median filter; 2D median filters; delays; feedforward paths; high sample rate semisystolic array architectures; latches; nonrecursive median filters; pipelining; processor; recursive median filters; Added delay; Computer architecture; Digital filters; Feedback; Frequency; Information filtering; Information filters; Pipeline processing; Sorting; Systolic arrays;
fLanguage
English
Journal_Title
Signal Processing, IEEE Transactions on
Publisher
ieee
ISSN
1053-587X
Type
jour
DOI
10.1109/78.277872
Filename
277872
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