Finite-difference time-domain analysis of flip-chip interconnects with staggered bumps

This paper presents finite-difference time-domain (FDTD) analysis of flip-chip interconnects. Transitions between coplanar waveguides on the chip and the mother board are investigated over a broad band of frequency by means of Fourier transform of the time-domain results. Objectives of the analysis include the evaluation of bump reflection and insertion loss as well as the reconfiguration of the transition to improve package performance. Novel designs have been developed and presented to reduce the effects of package discontinuities and asymmetry. Staggering the bumps has been found to reduce reflection and insertion loss over a broad band of frequency. A reduction In bump reflection of up to 8 dB per transition can be achieved by staggering the ground and signal connects. The degradation in package performance due to structure asymmetry is also studied. The present designs have also been found to reduce the effects of flip-chip asymmetry on insertion and reflection losses