Fault-tolerant design methodology for systolic array architectures

A systematic approach to the design of fault-tolerant VLSI systolic arrays is proposed. The approach comprises three steps. First, redundancies are introduced at the computation level by deriving different versions of the computation structure. This involves the modification of the dependency matrix (D) of an algorithm to reflect a given fault-tolerance requirement. Second, the dependency matrix of the respective version is mapped into arbitrarily large size VLSI systolic arrays, using space-time (S-T) mapping techniques. Finally, a fault-tolerant (FT) systolic array is constructed by merging the corresponding systolic array of the different versions of the computation. The scheme is applicable to any systolic array implementation and suitable for VLSI technology. The method is illustrated using the matrix multiplication algorithm