Optimised synthesis of delay-insensitive circuits using time-sharing

A syntax-directed translation procedure for the synthesis of truly delay-insensitive circuits from graph theoretic specifications is presented. In the synthesised circuit, for a given specification, different synchronisation structures (e.g. joins) in the specification are enforced by distinct circuit elements (e.g. C-elements). An attempt is made to enforce different synchronisation structures in a specification with the same circuit element so that the number of circuit elements in the synthesised circuit could be reduced. The circuit element is said to be `time-shared´ between the synchronisation structures in the specification. Theorems on when different synchronisation structures in a specification can time-share a circuit element are presented. An optimisation procedure based on such time-sharing is described. The optimisation procedure is illustrated with examples