In-situ phosphorous-doped VLPCVD polysilicon layers for polysilicon thin-film transistors

Polysilicon devices on glass substrates for large-area applications, such as poly-Si thin-film transistors in active-matrix displays, need a complete low-temperature process, especially to fabricate the drain and source polysilicon layers as well as the active channel layer. For this purpose, we have developed a very low pressure chemical vapour deposition process allowing in-situ phosphorous doping. By varying total pressure and phosphine/silane ratio, we control the doping concentration level over a large range (10¹⁸ to 5×10²⁰ cm^-3). Depending on deposition conditions, films are first amorphous or partially crystallised. The films are then fully crystallised by a 12 h in-situ vacuum annealing at 600°C. They are physically and electrically characterised. It is observed that in the 30 to 90 pascal pressure range, the dopant activation rate, electrical carrier mobility, and conductivity of the layers are optimised whatever the doping level. First runs of low temperature processed TFTs involving in-situ highly doped source and drain layers have given promising results