Title :
Large-area shower implanter for thin-film transistors
Author :
Wu, Y ; Montgomery, J.H. ; Refsum, A. ; Mitchell, S.J.N. ; Armstrong, B.M. ; Gamble, H.S.
Author_Institution :
Dept. of Electr. & Electron. Eng., Queen´´s Univ., Belfast, UK
fDate :
2/1/1994 12:00:00 AM
Abstract :
Solid-state diffusion and conventional ion implantation are not suitable for source and drain regions formation of polysilicon thin-film transistors on glass substrates. A 30 cm diameter large-area low-energy ion shower implanter with RIPE ion source and double-grid extraction system was developed as a possible low-cost solution. The ion beam current density for hydrogen plasma was 100 μA/cm2 for 3 keV implant energy, 300 W RF power, 140 gauss magnetic field and 3×10-4 mbar pressure. The uniformity of beam current density over the central 20 cm diameter was ±3.5%. Phosphorus implantation has been performed using a 15% PH3 in H2 gas mixture. Implantation at 3 keV for 5 min. results in an integrated dose of 2.48×1016 cm-2 with the concentration peak at a depth of 8.3 nm. Planar and mesa diodes fabricated on p-type silicon substrates have yielded fine rectifier characteristics. The shower implanter is thus suitable for TFTs source and drain region formation
Keywords :
current density; elemental semiconductors; insulated gate field effect transistors; ion implantation; phosphorus; semiconductor technology; silicon; thin film transistors; 140 gauss; 3 keV; 3*10-4 mbar; 30 cm; 300 W; H2; H2 plasma; P implantation; PH3; PH3-H2; PH3-H2 gas mixture; RF power; RIPE ion source; Si:P; double-grid extraction system; drain region formation; glass substrates; ion beam current density; large-area shower implanter; low-energy ion shower; p-type Si substrates; polycrystalline Si; polysilicon TFT; source region formation; thin-film transistors;
Journal_Title :
Circuits, Devices and Systems, IEE Proceedings -
DOI :
10.1049/ip-cds:19949826
