Title :
High-Q on-chip inductors using extremely thick silicon dioxide and copper-damascene technology
Author :
Tang, M. ; Li, H.Y. ; Zhang, Q.X. ; Liao, E.B. ; Yu, A.B. ; Lo, G.Q. ; Balasubramanian, N. ; Kwong, D.L.
Author_Institution :
Inst. of Microelectron., Singapore
Abstract :
High performance on-chip inductors fabricated using extremely thick low-stress silicon dioxide (SiO2) as the interface layer and copper damascene technology on standard CMOS silicon substrate are presented. A warpage-free low-stress SiO2 layer up to 20 mum thick is deposited using a modified deposition process. The maximum quality factor of a 1.3 nH inductor has been improved by 160% (from 21 to 55) when the thickness of SiO2 increases from 0.3 to 15 mum.
Keywords :
CMOS integrated circuits; CVD coatings; silicon compounds; thin film inductors; CMOS silicon substrate; SiO2; copper-damascene technology; extremely thick silicon dioxide; high-Q on-chip inductor; modified deposition process; warpage-free low-stress layer;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20083010
