Experimental operation of an RS flip-flop composed of nonlatching Josephson gates

Author

Mizugaki, Y. ; Onomi, T. ; Nakajima, K. ; Yamashita, T.

Author_Institution

Res. Inst. of Electr. Commun., Tohoku Univ., Sendai, Japan

Volume

6

Issue

2

fYear

1996

fDate

6/1/1996 12:00:00 AM

Firstpage

90

Lastpage

93

Abstract

We present the experimental implementation of an RS flip-flop (RS-FF) composed of dc-biased coupled-SQUID (C-SQUID) gates. The C-SQUID gate is a combination of a single-junction SQUID and a double-junction SQUID. This gate utilizes nonhysteretic Josephson junctions and it is operated in nonlatching mode with dc-biasing. Several logical functions are able to be realized with a C-SQUID gate by adjusting the input bias and the input signal levels. The speed performance of the gate is evaluated by simulation for ring oscillators, and the minimum switching delay of 6.5 ps/stage is obtained under Josephson critical current density of 10 kA/cm/sup 2/. We have fabricated the RS-FF composed of two C-SQUID NOR gates. The circuit is integrated using a Nb/AlO/sub x//Nb junction technology and its operation is demonstrated experimentally.

Keywords

Josephson effect; SQUIDs; aluminium compounds; critical current density (superconductivity); flip-flops; logic gates; niobium; superconducting device testing; superconducting logic circuits; type II superconductors; C-SQUID; Josephson critical current density; NOR gates; Nb-AlO-Nb; RS flip-flop; dc-biased coupled-SQUID; double-junction SQUID; input bias; input signal levels; minimum switching delay; nonhysteretic Josephson junctions; nonlatching Josephson gates; ring oscillators; single-junction SQUID; speed performance; Coupling circuits; Equivalent circuits; Flip-flops; Hysteresis; Josephson junctions; Logic gates; Niobium; SQUIDs; Superconducting logic circuits; Voltage;

fLanguage

English

Journal_Title

Applied Superconductivity, IEEE Transactions on

Publisher

ieee

ISSN

1051-8223

Type

jour

DOI

10.1109/77.506689

Filename

506689