Title :
A 7 Mbyte/s (65 MHz), mixed-signal, magnetic recording channel DSP using partial response signaling with maximum likelihood detection
Author :
Philpott, Rick A. ; Kertis, Robert A. ; Richetta, Ray A. ; Schmerbeck, Timothy J. ; Schulte, Donald J.
Author_Institution :
IBM Corp., Rochester, MN, USA
fDate :
3/1/1994 12:00:00 AM
Abstract :
A mixed-signal, 7.0 Mbyte/s PRML (partial-response maximum likelihood) read/write channel is discussed in this paper. PR-IV (minimum signal bandwidth) for signal encoding is used, along with ML (maximum likelihood) detection to achieve superior error rate performance. Signal equalization is provided using a programmable ten-tap FIR (finite impulse response) digital filter. This read/write channel is implemented on a single chip using analog circuits and 20 K CMOS logic gates. The 7.5 mm square chip uses a 5 V, 1 μm, BiCMOS process with a 6 GHz n-p-n and a 1 GHz p-n-p and is packaged in a 100-lead metal QFPK (quad flat pack)
Keywords :
BiCMOS integrated circuits; digital filters; digital signal processing chips; encoding; equalisers; magnetic recording; maximum likelihood estimation; mixed analogue-digital integrated circuits; signal detection; 1 micron; 5 V; 65 MHz; 7 Mbyte/s; BiCMOS process; CMOS logic gates; PRML read/write channel; analog circuits; error rate performance; finite impulse response; magnetic recording channel DSP chip; maximum likelihood detection; metal QFPK; mixed-signal processing chip; partial response signaling; programmable ten-tap FIR digital filter; quad flat pack; signal encoding; signal equalization; single chip implementation; Analog circuits; Bandwidth; CMOS analog integrated circuits; CMOS logic circuits; Digital filters; Digital signal processing; Error analysis; Finite impulse response filter; Magnetic recording; Maximum likelihood detection;
Journal_Title :
Solid-State Circuits, IEEE Journal of
