• DocumentCode
    1058185
  • Title

    Hot-carrier-reliability design guidelines for CMOS logic circuits

  • Author

    Quader, Khandker N. ; Minami, Eric R. ; Wei-Jen Ko ; Ko, Ping K. ; Hu, Chenming

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
  • Volume
    29
  • Issue
    3
  • fYear
    1994
  • fDate
    3/1/1994 12:00:00 AM
  • Firstpage
    253
  • Lastpage
    262
  • Abstract
    Long-term ring-oscillator hot-carrier degradation data and simulation results are compared to demonstrate that a circuit reliability simulator BERT can predict CMOS digital circuit speed degradation from transistor DC stress data. We present generalized hot-carrier-reliability design rules that translate device-level degradation rate to CMOS circuit lifetime. The design rules, which consist of lifetime and speed degradation factors, can roughly predict CMOS circuit degradation during the initial design, and can help reliability engineers to quickly estimate the overall product hot-carrier reliability. The NMOSFET and PMOSFET lifetime factors were found to obey 4/ftrise and 10/ftfall respectively. Typically, the NMOSFET and PMOSFET speed degradation factors are 1/4 and 1/2, respectively, with saturation region drain current as the monitor, while for a 100 MHz operating frequency and for an input rise time of 0.35 ns, the NMOSFET and PMOSFET time factors are 120 and 300, respectively
  • Keywords
    CMOS integrated circuits; circuit analysis computing; circuit reliability; hot carriers; integrated logic circuits; logic design; 0.35 ns; 100 MHz; BERT; CMOS circuit lifetime; CMOS logic circuits; NMOSFET; PMOSFET; circuit reliability simulator; design guidelines; design rules; digital circuit speed degradation; hot carrier reliability; long-term hot-carrier degradation data; ring-oscillator; saturation region drain current; transistor DC stress data; Bit error rate; CMOS digital integrated circuits; CMOS logic circuits; Circuit simulation; Degradation; Digital circuits; Guidelines; Hot carriers; MOSFET circuits; Predictive models;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/4.278346
  • Filename
    278346