Title :
A 300-MHz 16-b 0.5-μm BiCMOS digital signal processor core LSI
Author :
Nomura, Masahiro ; Yamashina, Masakazu ; Goto, Junichi ; Inoue, Toshiaki ; Suzuki, Kazumasa ; Motomura, Masato ; Koseki, Youichi ; Shih, Benjamin S. ; Horiuchi, Tadahiko ; Hamatake, Nobuhisa ; Kumagai, Kouichi ; Enomoto, Tadayoshi ; Yamada, Hachiro
Author_Institution :
Microelectron. Res. Labs., NEC Corp., Sagamihara, Japan
fDate :
3/1/1994 12:00:00 AM
Abstract :
A 300-MHz 16-b fixed-point digital signal processor (DSP) core LSI has been developed for video signal processing. In order to achieve high performance, the DSP core LSI employs a parallel processing architecture, 300-MHz redundant binary arithmetic units, and a sophisticated high-performance electrical design. The DSP core LSI, which was fabricated with 0.5-μm BICMOS and triple-level-metallization technology, has a 3.9 mm×4.6 mm area, and contains about 57K transistors. It consumes 2 W at a 300-MHz clock frequency with a 3.3-V power supply. Measured clock skew and critical path delay are less than 80 ps and 2.6 ns, respectively
Keywords :
BiCMOS integrated circuits; digital signal processing chips; large scale integration; parallel architectures; video signals; 0.5 micron; 16 bit; 2 W; 2.6 ps; 3.3 V; 300 MHz; 80 ps; BiCMOS; DSP core LSI; digital signal processor; fixed-point DSP; parallel processing architecture; redundant binary arithmetic units; triple-level-metallization technology; video signal processing; Arithmetic; BiCMOS integrated circuits; Clocks; Digital signal processing; Digital signal processors; Frequency; Large scale integration; Parallel processing; Power supplies; Video signal processing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
