3.3-V BiCMOS circuit techniques for a 120-MHz RISC microprocessor

Author

Murabayashi, Fumio ; Hotta, Takashi ; Tanaka, Shigeya ; Yamauchi, Tatsumi ; Yamada, Hiromichi ; Nakano, Tetsuo ; Kobayashi, Yutaka ; Bandoh, Tadaaki

Author_Institution

Res. Lab., Hitachi Ltd., Ibaraki, Japan

Volume

29

Issue

3

fYear

1994

fDate

3/1/1994 12:00:00 AM

Firstpage

298

Lastpage

302

Abstract

This paper describes 3.3-V BiCMOS circuit techniques for a 120-MHz RISC microprocessor. The processor is implemented in a 0.5-μm BiCMOS technology with 4-metal-layer structure. The chip includes a 240 MFLOPS fully pipelined 64-b floating point datapath, a 240-MIPS integer datapath, and 24 KB cache, and contains 2.8 million transistors. The processor executes up to four operations at 120 MHz and dissipates 17 W. Novel BiCMOS circuits, such as a 0.6-ns single-ended common base sense amplifier, a 0.46-ns 22-b comparator, and a 0.7-ns path logic adder are applied to the processor. The processor with the proposed BiCMOS circuits has a 11%-47% shorter delay time advantage over a CMOS microprocessor

Keywords

BiCMOS integrated circuits; VLSI; digital arithmetic; microprocessor chips; pipeline processing; reduced instruction set computing; 0.5 micron; 120 MHz; 17 W; 24 KB; 240 MFLOPS; 240 MIPS; 3.3 V; 4-metal-layer structure; 64 bit; BiCMOS circuit techniques; RISC microprocessor; cache; comparator; fully pipelined floating point datapath; integer datapath; logic adder; single-ended common base sense amplifier; Adders; BiCMOS integrated circuits; Bipolar transistors; CMOS technology; Logic circuits; Low voltage; MOSFETs; Microprocessors; Reduced instruction set computing; Wiring;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.278351

Filename

278351