A single poly EEPROM cell structure for use in standard CMOS processes

Author

Ohsaki, Katsuhiko ; Asamoto, Noriaki ; Takagaki, Shunichi

Author_Institution

Adv. Syst. Dev., IBM Japan Ltd., Shigaken, Japan

Volume

29

Issue

3

fYear

1994

fDate

3/1/1994 12:00:00 AM

Firstpage

311

Lastpage

316

Abstract

A single poly EEPROM cell structure implemented in a standard CMOS Process is developed. It consists of adjacently placed NMOS and PMOS transistors with an electrically isolated common polysilicon gate. The common gate works as a “floating gate”. The inversion layer as “control node (gate)”. Test chips which were fabricated in a 0.8 μm/150 Å standard CMOS logic process showed 5-9 V of threshold voltage shift and more than 10000 cycles of endurance with good data retention under high temperature. This EEPROM cell can be easily integrated with CMOS digital and analog circuits

Keywords

CMOS integrated circuits; EPROM; integrated memory circuits; silicon; 0.8 micron; 5 to 9 V; NMOS transistors; PMOS transistors; Si; common gate; control node; data retention; endurance; floating gate; high temperature; inversion layer; polysilicon gate; single poly EEPROM cell structure; standard CMOS processes; threshold voltage shift; CMOS logic circuits; CMOS process; Circuit testing; EPROM; Logic testing; MOS devices; MOSFETs; Standards development; Temperature; Threshold voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.278354

Filename

278354