A sampling technique and its CMOS implementation with 1 Gb/s bandwidth and 25 ps resolution

Author

Gray, C. Thomas ; Liu, Wentai ; Van Noije, Wilhelmus A M ; Hughes, Thomas A., Jr. ; Cavin, Ralph K., III

Author_Institution

Dept. of Electr. Eng., North Carolina State Univ., Raleigh, NC, USA

Volume

29

Issue

3

fYear

1994

fDate

3/1/1994 12:00:00 AM

Firstpage

340

Lastpage

349

Abstract

This paper presents a technique and circuitry for high-resolution sampling of a digital waveform. Very fine sampling resolution is achieved by simultaneously propagating both data and clock signals through delay elements in such a way that resolution is controlled by the difference in the delay of clock and data signals. Delay units were designed using biased CMOS and differential CMOS inverters. A sampler circuit with 64 stages has been fabricated in 1.2 μm CMOS technology, and test results show a bandwidth of up to 1 Gb/s for the input data and a sampling resolution externally adjustable between 25 and 250 ps. The fabricated circuit has shown sampling stability, monotonicity in sampling, and uniformity in sampling resolution

Keywords

CMOS integrated circuits; delay circuits; integrated logic circuits; signal processing equipment; 1 GHz; 1 Gbit/s; 1.2 micron; 25 to 250 ps; biased CMOS invertors; clock signals; data signals; differential CMOS inverters; digital waveform; high-resolution sampling; sampler circuit; sampling stability; sampling technique; Bandwidth; CMOS technology; Circuit testing; Clocks; Delay effects; Latches; Phase locked loops; Propagation delay; Sampling methods; Signal resolution;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.278359

Filename

278359